The present invention relates generally to the manufacture of high speed MOS semiconductor devices with improved transistor performance, and to MOS transistor devices obtained thereby. Specifically, the present invention relates to a method for fabricating MOS transistors with ultra-shallow depth source/drain extensions for providing improved device performance characteristics, which method utilizes strained lattice semiconductor substrates.
The escalating requirements for high density and performance associated with ultra-large-scale integration (ULSI) semiconductor devices require design features of 0.18 xcexcm and below, e.g., such as 0.15 xcexcm and 0.12 xcexcm, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 xcexcm and below challenges the limitations of conventional semiconductor materials and manufacturing techniques.
A problem associated with reduction of transistor design features to 0.18 xcexcm and below is the difficulty in forming ultra-shallow source/drain extension regions in conventional silicon (Si)-wafer based substrate materials. Specifically, ultra-shallow depth source/drain extensions having sufficiently low series resistance, thus high doping levels, are required for obtaining high quality transistor performance characteristics, including, inter alia, Ioff vs. Ion and saturation threshold roll-off voltage Vts. This problem is especially severe in the manufacture of p-channel MOS transistors comprising a boron (B)-containing p-type dopant species, largely due to the ease with which the small-sized boron atoms/ions diffuse in conventional Si-based semiconductor substrates.
As a consequence of the above-described and other shortcomings and drawbacks of conventional Si-based semiconductor substrates when utilized in the manufacture of ULSI semiconductor devices with design features below about 0.18 xcexcm, there recently has been much interest in various approaches with the aim or goal of developing new semiconductor materials which provide increased speeds of electron and hole flow therethrough, thereby permitting fabrication of semiconductor devices, such as integrated circuit (IC) devices with higher operating speeds, enhanced performance characteristics, and lower power consumption. One such material which shows promise in attaining the goal of higher device operating speeds is termed xe2x80x9cstrained siliconxe2x80x9d.
According to this approach, a very thin, tensilely strained, crystalline silicon (Si) layer (sometimes referred to as a xe2x80x9ccapxe2x80x9d layer) is epitaxially grown on a relaxed, graded composition Sixe2x80x94Ge buffer layer, which Sixe2x80x94Ge buffer layer in turn is formed on a suitable crystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI) wafer. Strained Si technology is based upon the tendency of the Si atoms, when epitaxially deposited on the Sixe2x80x94Ge buffer layer, to align with the greater lattice constant (spacing) of the Si and Ge atoms therein (relative to pure Si). As a consequence of the Si atoms being deposited on a substrate (Sixe2x80x94Ge) comprised of atoms which are spaced further apart, they xe2x80x9cstretchxe2x80x9d to align with the underlying Si and Ge atoms, thereby xe2x80x9cstretchingxe2x80x9d or tensilely straining the deposited Si layer. Electrons and holes in such strained Si layers have greater mobility than in conventional, relaxed Si layers with smaller inter-atom spacings, i.e., there is less resistance to electron and/or hole flow. For example, electron mobility/current flow in strained Si may be up to about 70% higher compared to electron flow in conventional Si. Transistors and IC devices formed with such strained Si layers can exhibit operating speeds up to about 35% faster than those of equivalent devices formed with conventional Si, without necessity for reduction in transistor size.
In view of the above, there exists a need for improved methodology for fabrication of high speed, sub-micron-dimensioned MOS transistors and CMOS devices which facilitates obtainment of the transistor performance advantages accruing from low series resistance, ultra-shallow depth source/drain extension regions not obtainable with conventional Si-based substrate materials, i.e., improved Ioff vs. Ion and Vts, and the enhanced device speeds attributable to the use of strained lattice semiconductor substrates.
The present invention, wherein high performance MOS transistors and CMOS devices comprising low series resistance, ultra-shallow depth source/drain extension regions, are formed in strained lattice semiconductor substrates by a process wherein the source/drain extension region depth is limited by the thickness of the xe2x80x9ccapxe2x80x9d layer, effectively overcomes problems associated with the manufacture of MOS transistors with ultra-shallow depth source/drain extension regions in conventional Si-based semiconductor substrates. As a consequence, the inventive methodology facilitates manufacture of high speed, high performance, reduced power consumption semiconductor devices utilizing strained semiconductor technology. Further the methodology afforded by the present invention enjoys diverse utility in the manufacture of numerous and various semiconductor devices and/or components therefor which require ultra-shallow junction depths and low series resistance for optimal performance.
An advantage of the present invention is an improved method for manufacturing a semiconductor device.
Another advantage of the present invention is an improved method of manufacturing a MOS transistor device with ultra-shallow depth source/drain extension regions.
Still another advantage of the present invention is an improved method of manufacturing a MOS transistor comprising a strained lattice semiconductor layer.
A further advantage of the present invention is an improved semiconductor device.
A still further advantage of the present invention is an improved MOS transistor having ultra-shallow depth source/drain regions.
A yet further advantage of the present invention is an improved MOS transistor comprising a strained lattice semiconductor layer.
Additional advantages and other aspects and features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the invention, the foregoing and other advantages are obtained in part by a method of manufacturing a semiconductor device, comprising sequential steps of:
(a) providing a semiconductor substrate including a pre-selected thickness strained lattice layer of a first semiconductor material at an upper surface thereof and an underlying layer of a second semiconductor material; and
(b) introducing a dopant-containing species of one conductivity type into at least one pre-selected portion of the strained lattice layer of first semiconductor material to form a dopant-containing region therein with a junction at a depth substantially equal to the pre-selected thickness, wherein the second semiconductor material of said underlying layer inhibits diffusion thereinto of the dopant-containing species from the strained lattice layer, thereby controlling/limiting the depth of the junction to substantially the pre-selected thickness of the strained lattice layer.
According to embodiments of the present invention, step (a) comprises providing a semiconductor substrate which further comprises a layer of a third semiconductor material beneath the layer of a second semiconductor material.
In accordance with preferred embodiments of the invention, the device comprises at least one MOS transistor, and step (a) comprises providing a MOS transistor precursor structure including a semiconductor substrate with at least one gate oxide/gate electrode layer stack on at least one portion of the upper surface of the substrate, the gate oxide/gate electrode layer stack including a pair of opposed side edges; and step (b) comprises introducing the dopant-containing species into exposed portions of the strained lattice layer to form at least one pair of shallow depth source/drain extension regions therein, each of the source/drain extension regions extending from just beneath a respective side edge of the gate oxide/gate electrode layer stack; and step (b) comprises introducing the dopant-containing species by ion implantation, with the at least one gate oxide/gate electrode layer stack serving as an implantation mask.
According to embodiments of the present invention, step (a) comprises providing a semiconductor substrate wherein the strained lattice layer has a thickness from about 25 to about 400 xc3x85; and step (b) comprises forming ultra-shallow source/drain extension regions having a junction depth from about 25 to about 400 xc3x85; whereas, according to certain preferred embodiments of the present invention, step (a) comprises providing a semiconductor substrate wherein the strained lattice layer has a thickness from about 50 to about 200 xc3x85; and step (b) comprises forming ultra-shallow source/drain extension regions having a junction depth from about 50 to about 200 xc3x85.
Embodiments of the present invention include the further step of:
(c) introducing dopant-containing species of the one conductivity type into portions of the shallow-depth source/drain extension regions to form deeper source/drain regions therein each having a junction within the third semiconductor layer; wherein step (c) includes forming sidewall spacers on each of the opposing side edges of the gate oxide/gate electrode layer stack and introducing the dopant-containing species in the portions of the source/drain extension regions by ion implantation, with the gate oxide/gate electrode layer stack with the sidewall spacers thereon serving as an implantation mask.
According to particular embodiments of the present invention, step (a) comprises providing a MOS transistor structure including a substrate wherein the strained lattice semiconductor layer of a first semiconductor material is a crystalline, epitaxial silicon (Si) layer from about 25 to about 400 xc3x85 thick, the underlying layer of a second semiconductor material is a crystalline, graded composition silicon-germanium (Sixe2x80x94Ge) layer from about 100 to about 300 xc3x85 thick, the crystalline, epitaxial Si layer being formed on the Sixe2x80x94Ge layer, and the layer of a third semiconductor material beneath the Sixe2x80x94Ge layer is a crystalline Si layer of a monocrystalline Si or silicon-on-insulator (SOI) material; and step (b) comprises forming at least one pair of shallow depth source/drain extension regions having a junction depth from about 25 to about 400 xc3x85, whereas, according to certain preferred embodiments of the present invention, step (a) comprises providing a MOS transistor structure including a substrate wherein the strained lattice semiconductor layer of a first semiconductor material is a crystalline, epitaxial silicon (Si) layer from about 50 to about 200 xc3x85 thick; and step (b) comprises forming at least one pair of shallow depth source/drain extension regions having a junction depth from about 50 to about 200 xc3x85.
In accordance with further preferred embodiments of the present invention, step (b) comprises implanting boron (B)-containing p-type dopant species at a dosage from about 1xc3x971014 to about 5xc3x971015 da/cm2 and an energy from about 100 eV to about 3 KeV, the at least one gate oxide/gate electrode layer stack serving as an implantation mask; and the method comprises further step (c) of forming sidewall spacers on each of the opposing side edges of the at least one gate oxide/gate electrode layer stack and implanting the boron (B)-containing p-type dopant species in exposed portions of the shallow-depth source/drain extension regions at a dosage from about 1xc3x971015 to about 1xc3x971016 da/cm2 and an energy from about 400 eV to about 5 KeV to form deeper source/drain regions each having a junction within the layer of third semiconductor material, the at least one gate oxide/gate electrode layer stack with the sidewall spacers thereon serving as an implantation mask.
Another aspect of the present invention is a method of manufacturing a MOS transistor device, comprising steps of:
(a) providing a semiconductor substrate including a pre-selected thickness strained lattice layer of a first semiconductor material at an upper surface thereof, an underlying layer of a second semiconductor material, and a layer of a third semiconductor material beneath the layer of a second semiconductor material;
(b) forming at least one gate oxide/gate electrode layer stack on at least one portion of the upper surface of said substrate, the gate oxide/gate electrode layer stack including a pair of opposed side edges;
(c) introducing a dopant-containing species into exposed portions of the strained lattice layer to form at least one pair of ultra-shallow depth source/drain regions therein, each of the source/drain extension regions extending from just beneath a respective side edge of the at least one gate oxide/gate electrode layer stack and having a junction at a pre-selected depth substantially equal to the pre-selected thickness of the strained lattice layer, wherein the second semiconductor material of the underlying layer inhibits diffusion thereinto of the dopant-containing species from the strained lattice layer, thereby controlling/limiting the depth of the junction to substantially the pre-selected thickness of the strained lattice layer, and
(d) introducing the dopant-containing species in exposed portions of the shallow-depth source/drain extension regions to form deeper source/drain regions each having a junction within the layer of third semiconductor material.
According to certain preferred embodiments of the present invention, step (a) comprises providing a substrate wherein the strained lattice semiconductor layer of a first semiconductor material is a crystalline, epitaxial silicon (Si) layer of pre-selected thickness from about 25 to about 400 xc3x85, the underlying layer of a second semiconductor material is a crystalline, graded composition silicon-germanium (Sixe2x80x94Ge) layer from about 100 to about 300 xc3x85 thick, the crystalline, epitaxial Si layer being formed on the Sixe2x80x94Ge layer, and the layer of a third semiconductor material beneath the Sixe2x80x94Ge layer is a crystalline Si layer of a monocrystalline Si or silicon-on-insulator (SOI) material; step (c) comprises forming ultra-shallow source/drain extension regions having a junction depth from about 25 to about 400 xc3x85; and step (d) comprises forming deeper source/drain regions having a junction depth from about 150 to about 1,000 xc3x85.
In accordance with certain preferred embodiments of the present invention, step (c) comprises forming ultra-shallow source/drain extension regions having a junction depth from about 50 to about 200 xc3x85; and step (d) comprises forming deeper source/drain regions having a junction depth from about 200 to about 1,000 xc3x85; wherein: step (c) comprises implanting boron (B)-containing p-type dopant species at a dosage from about 1xc3x971014 to about 5xc3x971015 da/cm2 and an energy from about 100 eV to about 3 KeV, the at least one gate oxide/gate electrode layer stack serving as an implantation mask; and step (d) comprises forming sidewall spacers on each of the opposing side edges of the gate oxide/gate electrode layer stack and implanting the boron (B)-containing p-type dopant species in exposed portions of the shallow-depth source/drain extension regions at a dosage from about 1xc3x971015 to about 1xc3x971016 da/cm2 and an energy from about 400 eV to about 5 KeV to form deeper source/drain regions each having a junction within the layer of third semiconductor material, the at least one gate oxide/gate electrode layer stack with the sidewall spacers thereon serving as an implantation mask.
Still another aspect of the present invention is a semiconductor device, comprising:
(a) a semiconductor substrate including a pre-selected thickness strained lattice layer of a first semiconductor material at an upper surface thereof, an underlying layer of a second semiconductor material, and a layer of a third semiconductor material beneath the layer of a second semiconductor material; and
(b) at least one dopant-containing region in at least one portion of the strained lattice layer, having a junction in the substrate at a depth substantially equal to the pre-selected thickness of the strained lattice layer, wherein the second semiconductor material of the underlying layer inhibits diffusion thereinto of the dopant-containing species from the strained lattice layer, thereby controlling/limiting the depth of the junction to substantially the pre-selected thickness of the strained lattice layer.
According to certain preferred embodiments of the present invention, the semiconductor substrate (a) comprises a crystalline, epitaxial silicon (Si) strained lattice semiconductor layer of pre-selected thickness from about 25 to about 400 xc3x85, the underlying layer of a second semiconductor material is a crystalline, graded composition silicon-germanium (Sixe2x80x94Ge) layer from about 100 to about 300 xc3x85 thick, the crystalline, epitaxial Si layer being formed on the Sixe2x80x94Ge layer, and the layer of a third semiconductor material beneath the Sixe2x80x94Ge layer is a crystalline Si layer of a monocrystalline Si or silicon-on-insulator (SOI) material; the dopant-containing species is a boron (B)containing p-type dopant, and the at least one dopant-containing region in the at least one portion of the strained lattice layer is at least one pair of ultra-shallow-depth source/drain extension regions of a p-channel MOS transistor, wherein the junction depth of the at least one pair of ultra-shallow-depth source/drain extension regions is from about 50 to about 200 xc3x85; and the MOS transistor further comprises: (c) at least one pair of deeper source/drain regions each with a junction within the layer of a third semiconductor material.